From 1175313fbd04d348a4410122e873f0c13af0e4fa Mon Sep 17 00:00:00 2001 From: Eric Yu Date: Thu, 12 Sep 2024 21:06:53 -0700 Subject: [PATCH] more generalized sim.do --- README.md | 13 ++++++++++++- src/hdl/CPU_pipelined.sv | 31 ++++++++++++++++++++++++++++--- tools/sim/runs/run1.do | 15 --------------- tools/sim/runs/run10.do | 15 --------------- tools/sim/runs/run11.do | 15 --------------- tools/sim/runs/run12.do | 15 --------------- tools/sim/runs/run2.do | 15 --------------- tools/sim/runs/run3.do | 15 --------------- tools/sim/runs/run4.do | 15 --------------- tools/sim/runs/run5.do | 15 --------------- tools/sim/runs/run6.do | 15 --------------- tools/sim/runs/sim.do | 16 ++++++++++++++++ 12 files changed, 56 insertions(+), 139 deletions(-) delete mode 100644 tools/sim/runs/run1.do delete mode 100644 tools/sim/runs/run10.do delete mode 100644 tools/sim/runs/run11.do delete mode 100644 tools/sim/runs/run12.do delete mode 100644 tools/sim/runs/run2.do delete mode 100644 tools/sim/runs/run3.do delete mode 100644 tools/sim/runs/run4.do delete mode 100644 tools/sim/runs/run5.do delete mode 100644 tools/sim/runs/run6.do create mode 100644 tools/sim/runs/sim.do diff --git a/README.md b/README.md index ad5417d..dd5ca27 100644 --- a/README.md +++ b/README.md @@ -19,4 +19,15 @@ LDUR Rd, [Rn, #Imm9]: Reg[Rd] = Mem[Reg[Rn] + SignExtend(Imm9)]. For lab #4 (only) the value in rd cannot be used in the next cycle. STUR Rd, [Rn, #Imm9]: Mem[Reg[Rn] + SignExtend(Imm9)] = Reg[Rd]. SUBS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] - Reg[Rm]. Set flags. -``` \ No newline at end of file +``` + +## How to simulate +1. Navigate to the `tools\sim\runs` directory. +2. Edit `bench_path` in `sim.do` to point to the desired benchmark (vector) file. +3. Run the simulation by executing `vsim -c -do sim.do -l vsim.log` in the terminal. + +To debug in waveform, run command +``` +modelsim -view vsim.wlf -do +``` + where `` is the path to the .do file containing the waveform settings. There are some in the `tools\sim\waves` directory. diff --git a/src/hdl/CPU_pipelined.sv b/src/hdl/CPU_pipelined.sv index 2f89d5b..624d30e 100644 --- a/src/hdl/CPU_pipelined.sv +++ b/src/hdl/CPU_pipelined.sv @@ -222,7 +222,8 @@ module CPU_pipelined #(parameter DELAY_NS=0.05) (reset, clk); endmodule - +// maximum number of cycles to run the simulation for. Exceeding this limit means something gets stuck in a loop. +`define MAX_CYCLES 1000000 module CPU_pipelined_testbench(); parameter ClockDelay = 5000; @@ -243,8 +244,32 @@ module CPU_pipelined_testbench(); reset <= 1; @(posedge clk); reset <= 0; @(posedge clk); // toggle reset - $display("%t begin benchmark", $time); - repeat(777) @(posedge clk); // repeat *many* times to give enough cycyles to calculate everything (~800 for sort) + $display("%t begin benchmark %s", $time, `BENCHMARK); + + i = 0; + // Continue until the halt instruction is reached or the simulation times out + while (dut.u_instructmem.instruction != 32'b00010100000000000000000000000000 && i < `MAX_CYCLES) begin + @(posedge clk); + i = i + 1; + end + repeat(5) @(posedge clk); + + if (i == `MAX_CYCLES) begin + $display("Simulation timed out"); + end + else begin + $display("Simulation completed in %0d cycles", i+1); + end + + for (i = 0; i < 32; i = i + 1) begin + $display("X%0d = %0d", i, dut.u_regfile.dataBus[i]); + end + + // Addtional signals to display + + // + + $display("PC = %0d", dut.pcIF / 4); $stop; end diff --git a/tools/sim/runs/run1.do b/tools/sim/runs/run1.do deleted file mode 100644 index 0d449b0..0000000 --- a/tools/sim/runs/run1.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test1.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run10.do b/tools/sim/runs/run10.do deleted file mode 100644 index 6471758..0000000 --- a/tools/sim/runs/run10.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test10.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run11.do b/tools/sim/runs/run11.do deleted file mode 100644 index f8b653d..0000000 --- a/tools/sim/runs/run11.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test11.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run12.do b/tools/sim/runs/run12.do deleted file mode 100644 index eca168b..0000000 --- a/tools/sim/runs/run12.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test12.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run2.do b/tools/sim/runs/run2.do deleted file mode 100644 index dac1c69..0000000 --- a/tools/sim/runs/run2.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test2.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run3.do b/tools/sim/runs/run3.do deleted file mode 100644 index d4978d8..0000000 --- a/tools/sim/runs/run3.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test3.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run4.do b/tools/sim/runs/run4.do deleted file mode 100644 index 0a13586..0000000 --- a/tools/sim/runs/run4.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test4.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run5.do b/tools/sim/runs/run5.do deleted file mode 100644 index 3bb58b6..0000000 --- a/tools/sim/runs/run5.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test5.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/run6.do b/tools/sim/runs/run6.do deleted file mode 100644 index 31416b7..0000000 --- a/tools/sim/runs/run6.do +++ /dev/null @@ -1,15 +0,0 @@ -vlib work - -vlog ../../../src/hdl/*.sv - -vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench - -do ../waves/test6.do - -view wave -view structure -view signals - -run -all - -# End diff --git a/tools/sim/runs/sim.do b/tools/sim/runs/sim.do new file mode 100644 index 0000000..46c19e7 --- /dev/null +++ b/tools/sim/runs/sim.do @@ -0,0 +1,16 @@ +# Change to path to the benchmark to simulate +set bench_path ../Benchmarks/test04_LdurStur.arm + +vlib work + +onerror {exit} + +vlog ../../../src/hdl/*.sv +define+BENCHMARK="${bench_path}" + +vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench + +log -r /* + +run -all + +quit -f \ No newline at end of file