From 0a176daddaddbdb2fba9f3f248679536ca161f8b Mon Sep 17 00:00:00 2001 From: Eric Yu Date: Thu, 18 Jan 2024 21:51:22 +0000 Subject: [PATCH] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 5f24623..921f2dc 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Simple ARM Pipelined CPU - +![ow](documents/469.jpg) ## Introduction A simple 64-bit ARM CPU with Pipelining. The pipelined CPU will have 1 delay slot after each load and branch instruction. The CPU instructions to be implemented are listed below. The data memory and instruction memory modules are provided in the files “datamem.sv” and “instructmem.sv” respectively. To simulate the CPU, head over to "tools/sim" irectory. Change the program loaded by editing the filename specified in “instructmem.sv”