69 lines
2.9 KiB
Plaintext
69 lines
2.9 KiB
Plaintext
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// Test of B.LT instruction.
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// Requires:
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// B.LT, SUBS, ADDI & B instructions
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// Expected results:
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// X0 = 1
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// X1 = 1
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//ADDI: I-type, Reg[Rd] = Reg[Rn] + {'0, Imm12}
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//OP Imm12 Rn Rd
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//3322222222 221111111111 00000 00000
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//1098765432 109876543210 98765 43210
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//1001000100 Unsigned 0..31 0..31
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//B: B-type, PC = PC + SignExtend({Imm26, 2'b00})
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//OP Imm26
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//332222 22222211111111110000000000
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//109876 54321098765432109876543210
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//000101 2's Comp Imm26
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//SUBS: R-type, Reg[Rd] = Reg[Rn] - Reg[Rm]
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//OP Rm Shamt Rn Rd
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//33222222222 21111 111111 00000 00000
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//10987654321 09876 543210 98765 43210
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//11101011000 0..31 000000 0..31 0..31
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//B.cond: CB-type, if (flags meet condition) PC = PC + SignExtend({Imm19, 2'b00})
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//OP Imm19 Cond
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//33222222 2222111111111100000 00000
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//10987654 3210987654321098765 43210
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//01010100 2's Comp Imm19 0..15
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//
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// Cond Name Meaning after SUBS FlagTest
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// 00000 EQ Equal Z==1
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// 00001 NE Not equal Z==0
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// 00010 HS Unsigned >= C==1
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// 00011 LO Unsigned < C==0
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// 00100 MI Minus N==1
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// 00101 PL Plus/0 N==0
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// 00110 VS Overflow V==1
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// 00111 VC No Overflow V==0
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// 01000 HI Unsigned > C==1 && Z==0
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// 01001 LS Unsigned <= C==0 || Z==1
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// 01010 GE Signed >= N==V
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// 01011 LT Signed < N!=V
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// 01100 GT Signed > Z==0 && N==V
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// 01101 LE Signed <= !(Z==0 && N==V)
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// 0111x AL Alway Always
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// MAIN:
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1001000100_000000000001_11111_00000 // ADDI X0, X31, #1 // X0 = 1, comparison target.
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1001000100_000000000000_11111_00001 // ADDI X1, X31, #0 // X1 = 0, only set to 1 if we get it all right.
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11101011000_00000_000000_00000_11111 // SUBS X31, X0, X0 // 1-1, not less than.
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01010100_0000000000000001000_01011 // B.LT ERROR // Don't take (+8)
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP
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11101011000_11111_000000_00000_11111 // SUBS X31, X0, X31 // 1 - 0, not less than.
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01010100_0000000000000000101_01011 // B.LT ERROR // Don't take (+5)
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP
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11101011000_00000_000000_11111_11111 // SUBS X31, X31, X0 // 0 - 1, is less than.
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01010100_0000000000000000100_01011 // B.LT SUCCESS // Take this. (+4)
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP
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// ERROR:
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000101_00000000000000000000000000 // B ERROR // Should never get here (0)
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP
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// SUCCESS:
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1001000100_000000000001_00001_00001 // ADDI X1, X1, #1 // Signal correct operation.
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// HALT:
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000101_00000000000000000000000000 // B HALT // Loop forever (0).
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP
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